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Yen-Fu Chen

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Accelerate RISC-V Instruction Set Simulation by Tiered JIT CompilationVMIL 20242024-10-20
Implements a RISC-V ISS that combines an interpreter, a fast tier-1 compiler, and an LLVM-based tier-2 compiler, claims faster interpreter performance than…
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RISC-V-Based Sandboxing for Secure and Efficient Software ExecutionLinuxCon @ Open Source Summit Japan 20232023-12-05
rv32emu is a compact ~10k‑line RV32 simulator that runs RV32IM ACF binaries, reduces memory footprint, and matches or beats Spike for interpreter-only…
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