Ching-Chun (Jim) Huang
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on a stage with
- Chao-Ting Linonce
- Chia-Heng Tuonce
- Ching-Shen Linonce
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| title | conference | date |
|---|---|---|
| Accelerate RISC-V Instruction Set Simulation by Tiered JIT Compilation | VMIL 2024 | 2024-10-20 |
Implements a RISC-V ISS that combines an interpreter, a fast tier-1 compiler, and an LLVM-based tier-2 compiler, claims faster interpreter performance than… | ||
| RON: One-Way Circular Shortest Routing to Achieve Efficient and Bounded-waiting Spinlocks | OSDI 2023 | 2023-07-10 |
RON uses a routing table and precomputes a shortest circular path to hand locks in a one-way circular routing among cores, turning lock handover into an online… | ||
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