The RISC-V Vector Cryptography Extensions

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" summary

RISC‑V adds a set of optional Vector Cryptography Extensions that define concrete instructions for AES, GHASH, SHA‑2, SM3, and SM4 and for bit-manipulation to accelerate SHA‑3; the spec targets 32 vector registers with vlen >= 128 bits and elen up to 64, uses element group size 4 or 8 to build 128‑ or 256‑bit lanes, introduces a vector‑scalar VSS variant to broadcast 128‑bit keys, and defines a GHASH opcode requiring a 128x128 carryless multiply; spec is near freeze.

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" chapters (9)

1. 0:00Introduction
2. 1:01Ken Dockser
3. 3:34Agenda
4. 4:15Cryptography
5. 5:53Vector Extensions
6. 9:36Element Groups
7. 13:35Vector Element Group Sizes
8. 14:53Vector scalar instruction
9. 15:38Vector cryptography extensions

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