RISC-V SoC Coherency: Dealing with Unique RISC-V Coherency Issues
summary
Breker’s Portable Stimulus test generator synthesizes self-checking coherency tests from a cache-protocol state machine, co-scheduling hundreds of sequences to produce cache line tearing and surface corner cases; it combines strategies like the Dekker algorithm with stride testing, targets the load/store subsystem that consumes about 80% of CPU cycles, and emits tests runnable in UVM simulation, emulator and post-silicon so the scenarios actually execute on hardware.
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chapters (13)
- 0:00Introduction
- 0:33Overview
- 1:04Functional Verification
- 1:52Challenges
- 2:05Unique Challenges
- 5:58Breker Verification Portfolio
- 8:13Why Breker
- 9:46Synthesis Approach
- 11:40Cache Line Tearing
- 12:03Creating Scenarios
- 13:51Breker History
- 14:58Fast Apps
- 15:49Questions
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