SystemVerilog Testbench linting with open-source
summary
An open-source lint framework built on slang/pyslang enforces SystemVerilog testbench rules written in Python, integrates into CI/CD like Git Actions, and ships customizable rule-sets for telecom and data-center flows. It catches concrete problems: deprecated DPI calls, mismatched C vs. sv signal directions, missing virtual interfaces in VIPs, and UVM quirks that hide bugs, and flags massive case ranges that would run billions of cycles; deployments to customers reduce late-find costs (up to ~50x at SOC integration) and generate manager-facing reports. UVM pitfalls
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chapters (11)
- 0:00Testbench linting intro
- 1:02Why linting matters
- 2:48UVM and testbench challenges
- 3:51Piseland linting approach
- 5:14Linting rules overview
- 6:18DPI checks case study
- 7:00Interface pitfalls
- 8:06UVM-specific linting
- 9:11Operator misuse
- 10:12Generating reports
- 10:58Q&A
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