ORConf 2023
who it's for
open source hardware contributors, chip designers, fpga developers, verification engineers, eda tool developers, RISC-V architects, security engineers, researchers and educators
topics
OpenROAD RTL-to-GDS flow; CologneChip GateMate FPGA module; snooping cache coherence for CVA6; SystemC TLM2 virtual prototypes; RADOPA optical probing simulation; mtime design approaches for RISC-V; WireGuard implemented in HDL; RDMA over Ethernet FPGA-to-GPU; Caliptra open source security IP; UVM and Verilator verification flow; cocotb Python-powered verification; SystemVerilog linting with Verible
| title | author | length |
|---|---|---|
| Opening | Stefan Wallentowitz | 24m |
History and logistics of the FOSSi Foundation and ORConf: two main conference days plus Sunday special sessions (TinyTapeout workshop, CocoDB unconference… | ||
| OpenROAD: The journey so far and roadmap | Andrew Kahng | 01h 00m |
OpenROAD is an open-source RTL-to-GDS tool that now produces manufacturable layouts for advanced finFET nodes and targets 24-hour RTL-to-GDS turnaround; the… | ||
| Module with CologneChip GateMate FPGA | Anton Kuzmin | 28m |
A pocket FPGA module based on the CologneChip GateMate FPGA is built, with PCB and KiCad files released under CERN‑OHL‑P and control code under MIT. The… | ||
| Old School cache coherence-a snooping system for a multicore processor based on CVA6 | M. Giacometti | 22m |
Project implements a low-latency snooping cache coherence unit for CVA6 cores, extending AXI to ACE over AXI and targeting quad-core use but prototyped as a… | ||
| Early performance estimation using virtual prototypes and open-source SW | Rocco Jonack | 20m |
Virtual prototypes based on SystemC TLM2 run full software stacks far faster than RTL sims and yield early architectural latency and bandwidth numbers. An… | ||
| Virtual Prototypes and Open Source Hardware Design in Research and Education | Sallar Ahmadi-Pour | 20m |
Open source RISC-V virtual prototype implemented in SystemC TLM 2.0 runs full OSes and claims 10x–100x faster than RTL for early software development; a… | ||
| RADOPA: Robustifying a Design Against Optical Probing Attacks | Sajjad Parvin | 22m |
RADOPA simulates backside optical probing during design by reading GDS layouts, convolving a Gaussian laser model with transistor polygons to produce activity… | ||
| OpenRISC update | Stafford Horne | 17m |
OpenRISC remains a 32-bit architecture with working 64‑bit FPU only on Mor1kx/OR1200 implementations, now exercising continuous CI: Verilator linting plus… | ||
| Visualizing and exploring open-source microchips | Thorsten Knoll | 17m |
Three manufacturable open PDKs (SkyWater 130, IHP 130, GF 180) drive open EDA work using OpenROAD/OpenLANE, KLayout, Magic and smaller tools; the workflow… | ||
| Effective Timekeeping in RISC-V Processors: Overview of mtime Design Approaches | Viktor Schneider | 22m |
RISC-V’s 64-bit mtime is memory-mapped but can be implemented four practical ways: trap-emulate CSR accesses (used by Ibex and NewRISC32) which is simple but… | ||
| Open Source Digital Design Tooling Updates | Karol Gugala | 21m |
CHIPS Alliance reports concrete tooling: an open SV Test suite runs SystemVerilog compliance across tools and shows most tests green; Verible supplies linting… | ||
| RISC-V Instruction Set Extensions for Cryptography - From Research to Standardization | F. Oberhansl | 16m |
RISC‑V already includes scalar crypto extensions ratified 2021 covering bit ops, carry‑less multiply, AES and SHA and data‑independent execution; AES… | ||
| Caliptra: Building Open Source Security IP with Open Source Tools | Michael Gielda | 14m |
Caliptra is an open-source root of trust developed jointly by Nvidia, Google, Microsoft and AMD and targets a near-term 1.0 RTL release intended for real-world… | ||
| overview and update | Greg Chadwick | 40m |
OpenTitan tapes out the Earl Grey engineering sample now in fab with over 30 blocks and nightly regressions running roughly 40,000 tests; repository totals… | ||
| GoIT: European initiative for free and open silicon | Rihards Novickis | 34m |
GoIT is an EU coordination project that drafts a pan‑jurisdiction hardware license, funds conferences and lawyers, and pushes policy feedback on the Chips Act… | ||
| Blackwire: WireGuard in HDL at 100+ Gbit/s | Leon Woestenberg | 22m |
Blackwire implements WireGuard as HDL/RTL for FPGA NICs and reaches 100 Gbits/s on the data path while keeping control on a RISC‑V core; the project is about… | ||
| Data transport in a radio telescope: Remote Direct Memory Access over Ethernet from FPGA to GPU | Stephen wonderful | 22m |
Radio telescope front ends stream huge continuous bursts of samples and the bottleneck is moving that traffic straight into GPU memory. Implementation of RoCE… | ||
| open source IP contributions | Reinier van der Walle | 16m |
ASTRON publishes the FPGA libraries and tooling behind UniBoard2 (four Arria 10 FPGAs) used as a filterbank, station beamformer and correlator, with FPGA code… | ||
| A reusable verification, emulation and validation flow for ASIC design | Tomasz Hemperek | 17m |
A reusable flow lets verification, firmware and software teams run the same tests against RTL simulation, FPGA emulation and eventual silicon so most work… | ||
| Open source design testing and verification with UVM and Verilator | Krzysztof Bieganski | 22m |
Verilator now supports many non‑synthesizable SystemVerilog features enabling near‑complete UVM use: full class hierarchy and parameter resolution for UVM (all… | ||
| How cocotb made Python-powered verification mainstream -- and what comes next | Philipp Wagner | 23m |
cocotb now ships 250 prebuilt wheels (simulator × Python × platform) so users no longer compile C++ at install time, and CI runs publicly against Questa… | ||
| SystemVerilog Testbench linting with open-source | Satinder Singh Paul | 15m |
An open-source lint framework built on slang/pyslang enforces SystemVerilog testbench rules written in Python, integrates into CI/CD like Git Actions, and… | ||
| MathLib - Math functions Library for SystemVerilog | Deepa Palaniappan | 17m |
MathLib implements a selection of MATLAB functions natively in SystemVerilog, published on GitHub as a reusable MathLib package that handles scalars, vectors… | ||
| spinal.lib.bus.tilelink : An Tilelink interconnect generator based on fiber | Charles Papon | 22m |
A Tilelink interconnect generator implemented in SpinalHDL uses fiber-based negotiation (user-space elaboration threads) to propagate and mutate parameters… | ||
| Ten Years of PULP: The Evolution of the Species from IoT to HPC | Davide Rossi | 58m |
Project PULP evolves from tiny IoT cores into cluster-based HPC demonstrators, producing multiple taped-out silicon generations (Vega, Marcellus, GAP9) and… | ||
| FuseSoC in Three Minutes | Olof Kindgren | 03m |
FuseSoC is a package manager for silicon that dates to 2011 and is already used by many high‑profile open source chips and several companies internally so it… | ||
| Renode - open source systems simulation framework | Michael Gielda | 03m |
Renode is an open‑source simulator that runs 280 real boards in simulation, models RISC‑V (including vectors and custom instructions) and ARM Cortex A/R 32/64… | ||
| Coriolis EDA Update | Rob Taylor | 03m |
Coriolis is a 20‑year EDA suite from the LIP6 lineage with a long‑standing Python API and built‑in mixed‑signal support; it claims compatibility with 90+… | ||
| SystemRDL and PeakRDL | Marek Pikuła | 03m |
SystemRDL is an Accellera open standard for register maps that already has a stable Python compiler on the SystemRDL GitHub and a suite of importer/exporter… | ||
| WaveDrom | Aliaksei Chapyzhenka | 03m |
A small toolchain that turns a JSON->SVG timing diagram description into images and register/field diagrams, with an online editor that gives a 300 ms live… | ||
| Tiny Tapeout Update | Matt Venn | 02m |
Tiny Tapeout 4 finishes with 143 submissions, totaling 2.6 meters of wire and 86,000 standard cells across 30 countries, but only half the tapeout array is… | ||
| Bluespec is my favourite HDL and here's why | Serge 'q3' Bazanski | 05m |
Bluespec HDL is presented through a concrete OpenMPW toy project that compiles to Verilog and runs under BlueSim simulation showing a GCD example and a… | ||
| SERV - A quick talk about a small CPU | Olof Kindgren | 03m |
A tiny RISC-V-like core uses a bit serial datapath and optional extensions with separate data and instruction buses and an extension interface, documented to… | ||
| Hardware: a messy landscape we all love | Michael Gielda | 02m |
A public Open Hardware Portal hosts dozens of open-source KiCad designs (permissive license) including FPGA, Nvidia and Snapdragon boards and supplies KiCad… | ||
| GateMate Module Crowdsourcing | Anton Kuzmin | 01m |
A tiny GateMate module is ready for small-scale manufacture, hardware design released under a permissive free license and available for anyone to produce; no… | ||
| pyfda: Python Filter Design and Analysis | Christian Muenker | 06m |
Live demo of pyfda designs a decimation filter from 48 kHz → 24 kHz with a required Nyquist stop at 12 kHz and a target -60 dB stopband, then generates… | ||
| nothing matches | ||