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Charles Papon

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spinal.lib.bus.tilelink : An Tilelink interconnect generator based on fiberORConf 20232023-09-15
A Tilelink interconnect generator implemented in SpinalHDL uses fiber-based negotiation (user-space elaboration threads) to propagate and mutate parameters…
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SpinalHDL : Paradigm introductionWeek of Open Source Hardware 20192019-06-13
SpinalHDL is a Scala library embedding HDL that generates Verilog by running Scala code as an elaborator, letting software data structures create repeated…
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SpinalHDL: Software generated hardwareORConf 20182018-09-21
SpinalHDL is a Scala-based DSL that emits synthesizable VHDL/Verilog netlists and runs as ordinary Scala code, not a separate compiler. It enforces explicit…
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