SpinalHDL : Paradigm introduction
summary
SpinalHDL is a Scala library embedding HDL that generates Verilog by running Scala code as an elaborator, letting software data structures create repeated hardware patterns. Examples include a memory-mapper generator that iterates a specification to emit address decode and read/write logic and can also emit a C header, and a VexRiscv flexible CPU built as plugins that scales from under 500 LUTs (tiny FPGA cores) up to ~2k LUTs Linux-capable cores and runs above 300 MHz on FPGA.
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chapters (9)
- 0:00Introduction
- 0:57SpinalHDL is embedded into a general purpose language
- 3:56Synergy between SpinalHDL and Scala
- 7:31Register bank: Using a specification
- 9:17Register bank : Defining a reusable tool
- 9:52Register bank : Tool usage
- 11:42Register bank: Hiding the tool internals
- 14:26Memory bus interconnect
- 18:58Some links
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