High-Level Synthesis of Functional Patterns with Lift
summary
Extends Lift with Lift to VHDL backend and new streaming and tiling patterns, generates synthesizable VHDL that runs on a Xilinx XC7Z010 prototype board, stores matrix A in on‑chip BRAM and streams B columns for matrix multiply, adds vectorization and coarse‑grained parallelism. Evaluation uses matrix multiplication and shows up to 10x speed‑up versus highly optimized CPU code and a vendor HLS flow. The generated designs synthesize and outperform the reference on this FPGA.
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chapters (13)
- 0:00Intro
- 1:24How to accelerate parallel programs?
- 2:18FPGA (Field-Programable Gate Array)
- 5:55The Goal
- 7:20The Power of LIFT
- 8:16The Challenge
- 9:01Streams - Basic Data Type
- 10:26Dot Product on FPGA
- 15:02Matrix Multiplication
- 17:28Evaluation
- 21:57Conclusion
- 24:58FPGA Utilization
- 29:21LIFT High-Level Patterns
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