Automated High-Level Synthesis Design Modularization via E-Graph Anti-Unification
summary
Framework automatically finds shared HLS modules by combining e-graph anti-unification with polyhedral loop analysis via the ISL integer sets library, generating loop-grouped rewrites and hardware-aware library learning adapted from Babel. Two cost functions guide extraction: a hardware impact cost for synthesizability and a hardware performance cost for PPA. Prototype finds common tiles and matrix multiply kernels, cuts multi-design area up to 46.1%, and improves search time from about 180s to 20s on tiled cases.
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chapters (12)
- 0:00Automated HLS modularization intro
- 3:11Design modularization in HLS
- 4:55Background on egraph anti-unification and Babel
- 6:17HLS design space with egraphs
- 8:03Polyhedral loop analysis
- 12:38Babel for hardware learning
- 13:42Hardware cost functions
- 17:12Decoupling hardware impact
- 19:19Results & case studies
- 21:03Scalability with polyhedral analysis
- 21:45Future HLS opportunities
- 24:10Q&A
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