Algorithm-Aware Hardware Optimization using E-Graph Rewriting: how should we marry(…)
summary
SEER orchestrates e-graph rewriting with LLVM MIR passes and an Act-based Intel Rover hardware optimizer, translating between MIR and a custom crand IR, applying dynamic rewrites, and enumerating alternate program representations. Each candidate is costed via source-level hardware estimators, regenerated to SystemC, and checked with a commercial equivalence checker. On benchmarks it finds significantly different pipelines and loop transformations, delivering up to 3.1x speedup and roughly 45% average improvement versus direct HLS at modest area/power tradeoffs.
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chapters (13)
- 0:00Algorithm-aware hardware optimization intro
- 1:05High-level synthesis challenges
- 3:35Hardware synthesis exploration
- 5:21Motivation for e-graph rewrites
- 6:26Seer: Super optimization Explorer
- 8:13Loop fusion with e-graphs
- 11:00Multi-level transformations in Seer
- 12:03Ensuring transformation correctness
- 13:09Evaluating hardware efficiency
- 14:13Unexpected e-graph benefits
- 17:27Nested loop optimization case study
- 18:52Future directions and challenges
- 20:18Q&A
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