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Theo Drane

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Automated High-Level Synthesis Design Modularization via E-Graph Anti-UnificationEGRAPHS 20252025-06-16
Framework automatically finds shared HLS modules by combining e-graph anti-unification with polyhedral loop analysis via the ISL integer sets library…
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Algorithm-Aware Hardware Optimization using E-Graph Rewriting: how should we marry(…)EGRAPHS 20242024-06-24
SEER orchestrates e-graph rewriting with LLVM MIR passes and an Act-based Intel Rover hardware optimizer, translating between MIR and a custom crand IR…
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Powered by Less: Low Power Circuit SynthesisEGRAPHS 20242024-06-24
An automated RTL-to-RTL framework named Rover uses e-graph rewriting to combine arithmetic rewrites with clock/data gating and transparent-register insertion…
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Novel Numerical Hardware Design Methodology - From machine readable spec to optimized RTLPLARCH 20232023-06-17
A machine-readable pipeline uses FPCore plus MPFR to simulate thousands of numeric-format variants in under two hours and generates a FPCore-to-bit-accurate…
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