Novel Numerical Hardware Design Methodology - From machine readable spec to optimized RTL
summary
A machine-readable pipeline uses FPCore plus MPFR to simulate thousands of numeric-format variants in under two hours and generates a FPCore-to-bit-accurate C-model that feeds HLS for early estimates; value-range analysis and an e-graph rewrite pass reduce a 277-bit naive datapath to about 25 bits and produce RTL that is both much faster and smaller than straight HLS output, implemented by a Rover super-optimizer targeting competitive final RTL.
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