Sirop: A Small IR for HLS with Parallel Patterns
summary
A minimal functional IR called Sirop expresses pipelining and spatial parallelism with five primitives and lowers map/zip/reduce as syntactic sugar, enabling rewrite-based fusion that removes pipeline registers. Hardware generation targets streamed handshake pipelines on FPGAs; compared to Aetherling, Shir and Intel HLS the designs use 76% fewer ALMs on average (61% and 68% reported against Aetherling and Shir) while matching latency at 175 MHz; compiler and artifacts are open and reproducible.
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chapters (19)
- 0:00Sirop introduction and goals
- 1:50Traditional HLS limitations
- 2:56Parallel patterns for streaming
- 4:24Rewrite rules for optimization
- 6:11Drawbacks of many patterns
- 7:36Sirop as small HLS IR
- 8:41Hardware model and pipeline
- 9:22Sirop examples: constant and stateful
- 10:48Stream map and zip in Sirop
- 11:52Handshake protocols in Sirop
- 12:33Stream reduce in Sirop
- 13:56Fusion optimization in Sirop
- 15:00Sirop vs prior HLS tools
- 16:44Summary and open-source
- 17:05Q&A: Sirop vs StreamHLS
- 18:50Q&A: Declarative vs cycle-accurate
- 19:13Q&A: Register usage and ALM
- 20:17Q&A: Fmax and latency
- 20:40Q&A: Hardest Sirop operator
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