LoopHint: A Compiler-Assisted Loop Branch Predictor for Embedded DSPs
summary
Compiler static analysis (LLVM SCEV plus a heuristic) extracts four deterministic loop patterns and emits LLVM SCEV + heuristic metadata lowered to two new RISC‑V loop hint instructions at machine SSA. Hardware adds a lightweight LIFO loop table that tracks bounds, iterators, nesting, age‑based retirement and stack invalidation. Evaluation on a gem5 RISC‑V core with DSP kernels and Embench‑IoT reports a 67% average misprediction reduction, up to ~90–98% on some kernels, with near‑zero MPKI on FIR and low area/power overhead.
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chapters (12)
- 0:00LoopHint project intro
- 2:08Deterministic loop prediction
- 3:15Loop patterns in DSP workloads
- 4:59LoopHint architecture overview
- 5:20Compiler analysis for loops
- 8:09ISA for loop hints
- 11:29Hardware loop predictor
- 13:38Nested loops and early breaks
- 14:00Performance evaluation
- 16:55Determinism benefits
- 17:37Conclusion and future work
- 18:18Q&A
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