Hikami: A Lightweight Hypervisor for Emulating RISC-V Extension Semantics with(…)

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Hikami is a lightweight Type‑1 hypervisor that traps only target RISC‑V instructions and CSRs to emulate extension semantics on real hardware (Milk‑V Megrez) using Sail-driven auto-generation of decoders and module templates. Evaluation on the ZBS bit‑manipulation extension shows ~300 instructions per trap, preserves 99.8% of native performance for non‑target workloads, keeps interrupt latency under 1 μs, generates 75% of code automatically (7k LOC total, 28 lines of hand‑written semantics) and runs up to 3.4× faster than QEMU when emulated ops are ≤0.1% of execution.

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" chapters (16)

1. 0:00Introduction
2. 1:08RISC-V ISA modularity gap
3. 3:13ISA extension validation challenges
4. 4:40Existing ISA emulation limits
5. 5:28Hikami design goals
6. 6:53Hikami emulation mechanics
7. 8:18Manual implementation risks
8. 8:39Formal specs automated framework
9. 10:06SAIL to hypervisor templates
10. 11:31Auto-generated decoders
11. 13:25Evaluation methodology
12. 14:26Performance on hardware
13. 15:31Code reduction gains
14. 15:54QEMU comparison
15. 16:36Summary and future
16. 17:20Q&A