Can Fine-Grain Multi-threading Subsume VLIW?
summary
Proposes a Synchronized Lane Architecture that maps each VLIW slot to a lock‑step lane with its own fetch and I‑cache, uses a single most‑significant suspend/resume SR bit per instruction to stop fetching, and a shared prepare‑branch PB register to update suspended lanes’ PCs. Builds a proof‑of‑concept ISA and simulator (AS‑OPT, Fast ADL) and runs long warmed runs (2B warm, 10B measured non‑meta instructions) on 4/8‑wide configs. Finds similar IPC to VLIW, notably lower instruction‑fetch energy and substantially smaller code size by eliminating most no‑ops.
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