A Functional Approach to Synthesizing Routable Programmable Accelerators for Neural(…)
summary
A functional IR uses Reduce and SwitchApply primitives plus upper-bounded streams to turn shared functions into programmable datapath+control that avoids per-call instantiation and routing blowup on FPGAs. The compiler targets an Intel Arria 10, emits an instruction stream with runtime length counters, and keeps large CNNs routable where previous let-based sharing fails. Evaluated on networks from LeNet-5 to ResNet (including TinyYOLO), designs remain synthesizable and show 1.1×–3.4× speedups versus prior functional-HLS approaches; artifacts and reproducible results are available.
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chapters (10)
- 0:00Introduction
- 2:49Why functional programming
- 4:36Mapping neural networks to FPGAs
- 8:10Function code to reduce primitives
- 10:19Variable shapes with upper bounding
- 13:53Multiple layer types with switch apply
- 15:40ResNet50 implementation
- 17:07Performance on Arria 10 FPGA
- 19:16Programmability and extensions
- 19:39Q&A
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