OLD VERSION: Building Abstractions at the Hardware-software Boundary
summary
Groq describes a deterministic spatial ISA and compiler that schedules every vector and hop at compile time, targeting a Tensor Streaming Processor with 320-element vectors, 220 MB on-chip at 80 TB/s and lockstep functional units; the compiler models travel time and resource allocation, produces cycle-accurate performance estimates, and drives hardware exploration (ISCA papers 2020/2022, ASAP BERT‑base results). Tools shown include an open FPGA toolchain analogy, a Groq view visualizer, and a chip-model where software-controlled memory and instruction dispatch <3% silicon enable kernel-free, predictable execution.
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chapters (10)
- 0:00Introduction to abstractions
- 8:46History of computer architecture
- 12:57GPUs and data flow compute
- 17:06Grok chip architecture overview
- 20:56Compiler challenges for spatial architectures
- 25:31Solving compiler challenges
- 31:54Concrete compiler example
- 43:09Compiler flow and hardware-software co-design
- 49:47Wrap-up and new golden age
- 52:11Q&A session
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