LCTES 2026
as the organisers put it
LCTES 2026 Welcome to the 27th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2026)! LCTES provides a link between the programming languages and embedded systems engineering communities. Researchers and developers in these areas are addressing many similar problems but with different backgrounds and approaches. LCTES is intended to expose researchers and developers from either area to relevant work and interesting problems in the other area and provide a forum where they can interact. LCTES 2026 is co-located with and shares the v ...
who it's for
compiler researchers and engineers, embedded systems engineers, programming language researchers, hardware and FPGA designers, binary and systems software engineers, formal verification researchers, machine learning researchers working on ML-hardware co-design, security and side-channel engineers
topics
profile-guided optimization with GCC and Clang; small IRs for HLS and FPGA pipelines; pointer ownership model for C with SAT checking; quantum machine learning with classical optimization; fine-grain multithreading as VLIW alternative; taxonomy of indirect jumps in RISC-V binaries; post-link basic block deduplication (DeduBB); lightweight hypervisor for RISC-V extension emulation; DSL-to-C for verifiable system code (Barocq); feature-aware causal compiler auto-tuning; event-chain-aware symbolic execution for serverless data flow; loop branch prediction for embedded DSPs
| title | author | length |
|---|---|---|
| Empirical Observations about Profile-Guided Optimizations for Mainstream C/C++ Compilers | Soma Pal, Prasad Anil Kulkarni | 29m |
Empirical study compares GCC and Clang PGO on MiBench x86-64 using 27 programs, 20 inputs each and an instrumentation-based offline PGO workflow; each… | ||
| Sirop: A Small IR for HLS with Parallel Patterns | Louis Hildebrand, Christophe Dubach | 22m |
A minimal functional IR called Sirop expresses pipelining and spatial parallelism with five primitives and lowers map/zip/reduce as syntactic sugar, enabling… | ||
| A Pointer-Ownership Model for C Inspired by Rust | David Svoboda, William Klieber, Lori Flynn, Ruben Martins, Jeffrey Hoskinson | 21m |
An end-to-end system builds per-function P models (ownership + lifetimes), uses an LLM-assisted builder to fill models, and checks them with a SAT solver that… | ||
| Practical Quantum Machine Learning: Overcoming the Bottlenecks of Scalability and(…) | Aviral Shrivastava | 01h 06m |
Claims a method called QPMeL that maps data onto independent unit spheres, replacing entangling circuits with minimal rotations so hardware needs two gates per… | ||
| Can Fine-Grain Multi-threading Subsume VLIW? | Scott Pomerville, Soner Önder, Gang-Ryung Uh, David Whalley | 24m |
Proposes a Synchronized Lane Architecture that maps each VLIW slot to a lock‑step lane with its own fetch and I‑cache, uses a single most‑significant… | ||
| On the Origins of Indirect Jumps in Embedded Software | Ariane Nicolas, Ronan Lashermes, Isabelle Puaut, Erven Rohou | 21m |
Systematic binary study produces a taxonomy of why indirect jumps appear and measures their prevalence on 32-bit RISC‑V binaries compiled from C, C++, Fortran… | ||
| Closing Session | Jeronimo Castrillon | 06m |
Quick conference wrap that announces distinguished reviewer awards: Klaus Schneider and Jong Uk Choi with Klaus to receive his by post and a photo taken with… | ||
| DeduBB: Binary Code Size Reduction via Post-Link Basic Block Deduplication | Chaitanya Mamatha Ananda, Mahbod Afarin, Rajiv Gupta, Sriraman Tallam, Han Shen, Xinliang David Li | 23m |
DeduBB is a post-link basic block deduplicator that replaces call/ret outlining with a save-and-jump sequence to deduplicate stack‑manipulating and… | ||
| Hikami: A Lightweight Hypervisor for Emulating RISC-V Extension Semantics with(…) | Norimasa Takana, Yoshihiro Oyama | 20m |
Hikami is a lightweight Type‑1 hypervisor that traps only target RISC‑V instructions and CSRs to emulate extension semantics on real hardware (Milk‑V Megrez)… | ||
| Towards Verifiable System Code using a DSL Compiled to Efficient and Readable C Code | Clément Chavanon, Henrik Karlsson, Frédéric Besson, Sandrine Blazy, Roberto Guanciale | 23m |
A minimal, purely functional DSL called Barocq compiles via Rocq to readable C by enforcing a strict alias-control discipline so the compiler does zero-cost… | ||
| Opening Remarks | Jeronimo Castrillon | 09m |
Remarks summarize conference stats and schedule: 42 full papers and 12 short papers yield 196 reviews (≈3.6 per paper) with each TPC member reviewing 5–7… | ||
| CausalTuner: Feature-Aware Causal Guidance for Compiler Auto-tuning | Jiaqing Zhong, Juan Chen, Yichang Zhou, Kuan Li | 19m |
Framework applies LLVM-based tuning on AMD hardware, extracts program features from optimized bitcode, clusters similar programs with synergy clustering, runs… | ||
| SymFlow: Event-Chain-Aware Symbolic Execution for Serverless Sensitive Data Flow(…) | Yuanpeng Wang, Zhineng Zhong, Zhenkai Liang, Ding Li, Yao Guo, Xiangqun Chen | 20m |
SymFlow combines static architectural analysis to build an event dependency graph with inter-function event-sensitive symbolic execution that emulates cloud… | ||
| A Programming Model for Efficient Inter-Kernel Control-Flow on Memory-Mapped Near-Data(…) | Seungheon Lee, Wonhyuk Yang, Seonyeong Heo, Gwangsun Kim | 10m |
Arachne is a programming model that moves control flow onto a memory‑mapped NDP device by introducing a device_main routine and C++ NDP task classes, extending… | ||
| Bridging the Memory Hotness Gap in Edge Systems with Hotness-Segregated Object Allocation | Ruizhe Huang, Jiahua Wang, Qihang Xu, Peng Jiang, Zhida An, Ding Li, Yao Guo, Xiangqun Chen, Yuxin Ren, Ning Jia | 25m |
HotMalloc reallocates objects by hotness instead of size, using profile-guided optimization to learn access counts offline and an offset-encoded call-site… | ||
| LoopHint: A Compiler-Assisted Loop Branch Predictor for Embedded DSPs | Yuanyang Xiang, Chen Xu, Ruozhou Xiao, Zhiwei Zhang | 20m |
Compiler static analysis (LLVM SCEV plus a heuristic) extracts four deterministic loop patterns and emits LLVM SCEV + heuristic metadata lowered to two new… | ||
| MemSpec: Memory-Aware Runtime for Adaptive Draft Scheduling in Speculative Decoding on(…) | Eunjeong Kim, Yeong Jun Jeon, Myeonggyun Han | 18m |
Runtime called MemSpec implements a lightweight predictor, a draft-model cache manager and a runtime controller on a Jetson Orin Nano, running 7B target models… | ||
| Scheduled Partial-Credit RL for Reliable Code Generation with Small Language Models (WIP) | Suryansh Singh Sijwali, Suman Saha | 13m |
A reliability-first pipeline uses LoRA supervised finetuning (≈60M of 1.3B params) then PPO with a joint reward: staged functional partial credits (syntax… | ||
| A Functional Approach to Synthesizing Routable Programmable Accelerators for Neural(…) | Tzung-Han Juang, Paul Teng, Christophe Dubach | 21m |
A functional IR uses Reduce and SwitchApply primitives plus upper-bounded streams to turn shared functions into programmable datapath+control that avoids… | ||
| CVS: A Metric for Security-Aware Compilation against Side-Channel Attacks in Edge SoCs(…) | Yi Han, Puhong Lei, Yang Shi, Zhe Li, Xing Mou, Jianjun Chen, Yaohua Wang | 07m |
Paper proposes a numeric metric, Confusion Variance Score (CVS), that quantifies how compilation choices change DRAM-access time-series and thus side-channel… | ||
| nothing matches | ||