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Ronan Lashermes

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titleconferencedate
On the Origins of Indirect Jumps in Embedded SoftwareLCTES 20262026-06-15
Systematic binary study produces a taxonomy of why indirect jumps appear and measures their prevalence on 32-bit RISC‑V binaries compiled from C, C++, Fortran…
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Lightning Talk: Timesecbench: A Work in Progress Benchmark Suite to Assess Timing...RISC-V Forum: Security 20212021-04-14
timesecbench is a portable microarchitectural timing-leakage benchmark suite implemented for RISC‑V cores that currently supplies four benchmarks targeting L1…
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