Lightning Talk: Timesecbench: A Work in Progress Benchmark Suite to Assess Timing...
summary
timesecbench is a portable microarchitectural timing-leakage benchmark suite implemented for RISC‑V cores that currently supplies four benchmarks targeting L1 data cache, L1 instruction cache, BTB and BHT gadgets and measures timing via covert‑channel matrices. Benchmarks use alignment and volatile tricks to reduce fetch and compiler noise, run deterministically on local RISC‑V cores, and produce timing matrices for later conversion to a channel matrix and capacity estimate. Missing: multicores, RAS/PHT tests and robust non‑deterministic metrics.
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