Securing High-performance RISC V-Processors from Time Speculation
summary
Claims that RISC-V cores can remain high‑performance while blocking speculation‑based timing leaks without ISA changes, backed by measurements that about 25% of instructions are past the point of no return. Concrete mitigations include delay predictor updates until commit, buffer speculative cache fills in the store‑completion buffer and allocate directly to L1, avoid speculative updates to shared resources, and handle variable‑latency units (e.g. FP sqrt) and BTB/partitioning strategies to prevent cross‑domain contention.
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chapters (9)
- 0:00Introduction to Spectre attacks
- 1:46High-performance secure processors
- 5:59Mitigation techniques overview
- 8:11Cache and predictor updates
- 10:19Shared resource contention
- 12:23Preventing speculative leaks
- 13:30Resource flushing strategies
- 14:31RISC-V security recommendations
- 15:35Q&A
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