GDB for RISC-V: Extending Support for Bare Metal Multi-core Debugging

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" summary

GDB has basic bare-metal RISC‑V support upstream since 6 March, providing register/memory access, start/stop and ABI-aware unwinding; testing shows a better than 99% pass rate on the built‑in simulator and lower but comparable results against a remote GDB server. Work in progress adds XML target description and memory‑map and remote‑IO support, stack unwinding without DWARF, and upstreaming an ISS; multi‑core non‑stop debugging is exercised on a 36‑core RV64 test system with remaining address‑space and link‑register ABI issues.

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" chapters (8)

1. 0:00Intro
2. 0:33GDB in the RISC-V World
3. 2:42GDB Regression Tests (Sim Subset)
4. 3:18GDB Regression Tests (GDBserver Subset)
5. 5:42Upstream GDB Next Steps
6. 6:29GDB Historic View of Multicore Debug
7. 7:33GDB Future View of Multicore Debug
8. 9:19Current Status

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