BASE ISA

on YouTube ↗38m

" summary

Design defines RV32I: 31 general-purpose registers with x0 hardwired to 0 and a 32-bit PC, six main instruction formats with 12-bit and 20-bit immediates so immediates sign-extend and can be composed (LUI+ADDI) for full 32-bit addresses. Multiply/divide move to M extension: eight multiply/divide/remainder ops, atomics provide LR/SC plus scalable AMO ops with acquire/release bits, floating point follows IEEE754 with 32 FP registers, and code-size wins come from C extension: 16-bit compressed encodings that map common 32-bit idioms into half-size instructions.

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" chapters (16)

1. 0:00Introduction
2. 0:26Genesis of RISC-V
3. 1:14Problems with x86 ISA
4. 2:55Problems with ARM ISA
5. 4:26RISC-V Development
6. 5:19Architectural State
7. 7:19Integer Arithmetic
8. 10:10Loads and Stores
9. 12:15Global Addressing
10. 14:04Conditional Branching
11. 16:28Unconditional Jumps
12. 20:13Base ISA Variants
13. 23:27M-Extension
14. 25:46A-Extension
15. 30:24F and D Extensions
16. 33:13C-Extension

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