RISC-V Support for Persistent Memory Systems
summary
Proposes adding uncacheable load/store ops (byte/half/word variants) so writes can bypass caches, a CLWB cache-line write-back that does not invalidate, and an SFENCE store-fence for durable ordering; shows workarounds today fail (Whisper benchmark suite of 10 apps will not compile for RISC-V), cites persistent filesystems like NOVA and hardware undo/redo designs that require these primitives, and demonstrates a path to connect RTL (Rocket/BOOM) to an FPGA board to measure area/cycle/energy for persistent-memory prototypes.
AI-written summary · about
chapters (7)
- 0:00Introduction to talk
- 1:03Persistent memory support needs
- 2:28New RISC-V instructions proposed
- 4:59Implementation in RISC-V system
- 7:10Impact on persistent memory research
- 10:19Western Digital work relevance
- 12:09Q&A: Why non-volatile memory needs special instructions
related talks
15mEnabling High-Performance Storage for RISC-V
17mPreview: Persistent Memory
43mPromise and Pitfalls of Persistent Memory
01h 07mEmerging Embdedded Memories and Storage
35mDeveloping Software for Persistent Memory
01h 08mC++ and Persistent Memory Technologies, Like Intel's 3D-XPoint
35mDeveloping Software for Persistent Memory
16mJohnny Cache: the End of DRAM Cache Conflicts (in Tiered Main Memory Systems)