Processor Trace in a Holistic World
summary
Branch-compressed branch trace for RISC-V emits a bit-vector branch map of taken/not-taken and only sends full addresses on unpredictable PC changes, reducing bandwidth; encoder exposes encoder interface fields (instruction, PC, exception/interrupt cause, privilege) and emits four message types (update, differential, full destination, sync). Filtering supports address ranges, privilege levels, ISR-only and event-triggered capture. Demo captures ARM and RISC‑V cores into an IDE with packet text and bus bandwidth visuals; a task group plans to standardize the packet format and interface.
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chapters (12)
- 0:00Introduction
- 0:49The Problem
- 2:30Branch Trace
- 3:35Interrupts
- 4:25Interface
- 5:33Encoder
- 6:03Algorithm
- 6:45Filtering
- 7:32Benchmarks
- 8:17Holistic SOC
- 11:00Summary
- 11:47Next Steps
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