8th RISC-V Workshop Barcelona 2018
| title | author | length |
|---|---|---|
| RISC V ISA & Foundation Overview | Rick O'Conner | 19m |
Origins in 2010 lead to a Foundation in August 2015 that owns the spec, the compliance test suites and the trademark; the ISA is deliberately modular extension… | ||
| BASE ISA | Andrew Waterman | 38m |
Design defines RV32I: 31 general-purpose registers with x0 hardwired to 0 and a 32-bit PC, six main instruction formats with 12-bit and 20-bit immediates so… | ||
| Privileged ISA | Allen Baum | 38m |
RISC-V privileged ISA defines hierarchical modes (user, supervisor, machine, debug) with 4k CSR address space divided as 1k per mode, mode-specific CSRs and… | ||
| Memory Model | Daniel Lustig | 32m |
RISC-V defines an RVWMO memory model with axiomatic and operational models side-by-side, a concrete litmus example (message passing) and a practical… | ||
| Vector ISA | Roger Espasa | 36m |
RISC-V adds 32 vector registers V0–V31, a programmable VL register that limits active elements, and a V-config that selects register count and element width… | ||
| Debug Specification | Gajinder Panesar | 32m |
A RISC‑V debug specification defines a debug module with mandatory abstract commands to read/write GPRs, optional FPR/CSR access, an optional program buffer… | ||
| Formal Specification | Thomas Bourgeat | 31m |
Formal RISC‑V semantics implemented as a configurable, monadic Haskell monadic spec that leaves low‑level ops (get/set reg, memory I/O) abstract so the same… | ||
| LLVM for RISCV | Alex Bradbury | 28m |
Describes adding bit-manipulation ops to the LLVM RISC-V backend with working RV32 and RV64 support now upstream, claiming parity with GCC for code size on the… | ||
| Welcome Address & Foundation Overview | Rick O'Conner | 12m |
Foundation overview and logistics: the nonprofit governing the RISC‑V specs reports growth from ~16 members in 2016 to 150+ members today (about 97… | ||
| State of the Union: RISC-V | Krste Asanovic | 26m |
Project starts in 2010 and establishes a frozen base ISA with modular extensions, first tape out in 2011 and a Linux port shortly after; foundation forms in… | ||
| The State of RISC V Software | Palmer Dabbelt | 25m |
RISC‑V now runs a usable Linux system on commodity boards: a HiFive Unleashed boots Debian and Fedora from SSD and runs X and browsers with hardware GPU… | ||
| Vector ISA Proposal Update | Roger Espasa | 30m |
Register-type encoding moves out to an optional extension and the base uses a more classical opcode-driven type scheme; register-type extension moved to an… | ||
| The RISC-V Formal Specification Technical Group: Progress Report | Rishiyur Nikhil | 20m |
Working group of about 10–15 regular members produces a machine-readable ISA semantics implemented in Haskell (MIT variant) that runs ELF/memory images as an… | ||
| RISC V Memory Consistency Model Task Group Update | Daniel Lustig | 15m |
Task group upstreams a concrete memory model: RVWMO baseline defines same-address ordering, load-value, atomicity (LR/SC) and a progress axiom, plus syntactic… | ||
| Keynote: Software Drives Hardware, lessons learned and future directions | Robert Oshana | 21m |
Company integrates RISC‑V into microcontroller flow using Chisel to prototype instruction extensions; one embedded engineer produces custom instructions to… | ||
| Keynote: Unleashing the Power of Data with RISC-V | Martin Fink | 39m |
Western Digital prototypes two in-house RISC‑V cores (a tiny and a small) targeted at SSD controllers, each implemented as a 2-way superscalar in‑order core… | ||
| RISC-V Debugging: Custom ISA Extensions, Multicore, DTM Variants | Markus Götzle | 14m |
Lauterbach describes concrete support for RISC-V debugging using the Trace32 toolset including a hardware debug module and off-chip trace units, a claim of 40%… | ||
| GDB for RISC-V: Extending Support for Bare Metal Multi-core Debugging | Jeremy Bennett | 10m |
GDB has basic bare-metal RISC‑V support upstream since 6 March, providing register/memory access, start/stop and ABI-aware unwinding; testing shows a better… | ||
| A Common Software Development Environment for Many-core RISC-V based Hardware and Virtual Platforms | Gajinder Panesar, Simon Davidmann | 15m |
Imperas provides an instruction‑accurate simulator that boots Linux in under 10 seconds on a modeled SiFive U54 class core, models peripherals with real‑time… | ||
| HiFive Unleashed: World's First Multi-Core RISC-V Linux Dev Board | Yunsup Lee | 17m |
A 64-bit RISC‑V Linux dev board ships a FU540 SoC with four U54 application cores plus one E51 core running at 1.5 GHz, a 2 MB banked L2, and 8 GB DDR4 on the… | ||
| HiFive Unleashed Expansion Options and Capabilities | Ted Marena | 16m |
Expansion kit attaches to the HiFive Unleashed via an FMC and exposes a Microsemi PolarFire FPGA PolarFire FPGA (300,000 LEs) plus a preloaded PCIe root… | ||
| Simulating Heterogeneous Multi-node 32-bit and 64-bit RISC-V Systems Running Linux and Zephyr | Michael Gielda, Annemarie Labath | 14m |
Renode simulates a heterogeneous four-node setup with mixed 32‑bit and 64‑bit RISC‑V cores running Linux and Zephyr concurrently, boots two Linux instances in… | ||
| Debian GNU/Linux Port for RISC-V 64-bit | Bastian A. Germann | 24m |
Debian adds a 64-bit RISC-V port that bootstraps from a cross-compiled seed and is imported into Debian infrastructure, targeting RV64GC baseline with Linux +… | ||
| Fedora on RISC-V | Richard Jones | 14m |
Fedora builds a RISC‑V port by bootstrapping over two months, compiling 16,700 packages into ~12,700 binaries and running parallel Rawhide and Fedora 28 builds… | ||
| Smallest RISC-V Device for Next-Generation Edge Computing | Yunsu Choi | 15m |
A 14 nm RISC‑V system shrinks a processor die to ~0.07 mm² with a separate 32 KB SRAM die (~0.04 mm²) and a <1 mm² silicon interposer using 20 µm bumps for… | ||
| Video: The MareNostrum | Sergi Girona | 07m |
MareNostrum is a chapel‑installed supercomputer delivering 13.7 petaflops total across 3,456 nodes with about 390 TB memory and a 1.3–1.5 MW power envelope… | ||
| Poster / Demo Previews | Derek Atkins, Mary Bennett, Ekaterina Berezina, Andrey Smolyarov, Alex Bradbury, Luca Carloni, Christian Palmiero, Jie Chen, Matt Cockrell, Alberto Dassatti, Christian Fabre, Juan Fumero, Nicolas Gaude, Hai Yu, Chris Jones, Zdenek Prikryl, Felix Kaiser, Alexander Kamkin, Andrei Tatarnikov, Luke Kenneth Casson Leighton, Heng Lin, Maja Malenko, Eric Matthews, Lesley Shannon, Paulo Matos, Lucas Morais, Mauro Olivieri, Aleksandar Pajkanovic, Matheus Ogleari, Shubhodeep Roy, Boris Shingarov, Christoph Schulz, Wei Song, Rui Hou, Dan Meng, Greg Sullivan, Robert Trout, Vasily Varaksin, Danny Ybarra | 01h 12m |
Poster session previews list concrete results and demos to see: a quantum‑resistant secure boot shows large speedups on HiFive hardware; CGEN generates… | ||
| Fast Interrupts for RISC-V | Krste Asanovic | 31m |
New task group defines concrete fast-interrupt changes: add configurable per-interrupt privilege/mode, preemption level (3–7 suggested) and priority, provide… | ||
| RISC-V DSP (P) Extension Proposal | Chuan Hua Chang, Richard Herveille | 16m |
Proposal defines a RISC-V GPR-based SIMD DSP extension (packed 8/16/32-bit lanes plus non-SIMD 16/32/64 ops) with saturation, rounding and fixed-point support… | ||
| RISC-V ISA Cryptographic Extensions Proposal Summary | Richard Newell | 11m |
RISC-V cryptographic extension work proposes using the vector extension registers to hold multiword values and perform long-arithmetic primitives for bignum… | ||
| Formal Assurance for RISC-V Implementations | Daniel Zimmerman, Joseph Kiniry | 28m |
Galois applies mechanized specs and formal proofs to RISC-V, compiling Haskell specs with Clash→Verilog and checking RTL equivalence with JasperGold… | ||
| Undefined, Unspecified, Non-deterministic, and Implementation Defined Behavior | Clifford Wolf | 13m |
Taxonomy of specification holes compares undefined behavior, undefined values and non-determinism and shows why both undefined forms break falsifiability: a… | ||
| Foundational HPC Systems for 2020 and Beyond | Steven Wallach | 14m |
Proposes a concrete path to RV128 with segmented 128-bit virtual addresses to address more than an exabyte, preserve RV64 binary compatibility via 64→128… | ||
| Keynote: European Processor Initiative & RISC-V | Mateo Valero | 39m |
European Processor Initiative describes building a European CPU and accelerator stack for HPC and supercomputers using RISC‑V core design plus vector +… | ||
| Securing High-performance RISC V-Processors from Time Speculation | Chris Celio | 17m |
Claims that RISC-V cores can remain high‑performance while blocking speculation‑based timing leaks without ISA changes, backed by measurements that about 25%… | ||
| Use of RISC-V on Pixel Visual Core | Matt Cockrell | 14m |
Evaluation integrates the PULP RI5CY RV32IMC core as a local microcontroller inside Pixel Visual Core to handle job scheduling and DMA control; choice favors… | ||
| Linux-Ready-RV GC AndesCore with Architecture Extensions | Charlie Su, Andrei Tatarnikov | 16m |
Andes ships a family of RISC-V cores (32- and 64-bit N25 series) with a configurable 5-stage pipeline, optional branch prediction, local cache with parity/ECC… | ||
| Processor Trace in a Holistic World | Ciprian Pascu | 16m |
Branch-compressed branch trace for RISC-V emits a bit-vector branch map of taken/not-taken and only sends full addresses on unpredictable PC changes, reducing… | ||
| RISC-V Meets 22FDX: an Open Source Ultra-low Power Microcontroller Platform | Pasquale Davide Schiavone, Sanjay Charagulla | 17m |
An open-source PULP microcontroller is taped out in GlobalFoundries 22FDX as the Quentin chip, a 2.3 mm² die with 1.2 mm² effective logic area that combines a… | ||
| Ariane: An Open Source 64-bit RISC-V Application Class Processor and latest Improvements | Pablo Odriozola | 21m |
Ariane is a 64-bit RISC-V application core that implements the privileged spec and targets Linux, occupying about 185 kilo gates with a six‑stage in-order… | ||
| RISC-V Support for Persistent Memory Systems | Krzysztof Dróżdż | 18m |
Proposes adding uncacheable load/store ops (byte/half/word variants) so writes can bypass caches, a CLWB cache-line write-back that does not invalidate, and an… | ||
| The Hybrid Threading Processor for Sparse Data Kernels | Tony Brewer | 19m |
A RISC‑V based RV64G core array with custom thread and message instructions implements a high‑thread barrel processor that pauses threads waiting on memory and… | ||
| How PULP-based Platforms are Helping Security Research | Frank K. Gürkaynak | 17m |
Presentation by Frank Gürkaynak at ETH Zurich on May 9, 2018 at the RISC-V Workshop in Barcelona, hosted by Barcelona Supercomputing Center and Universitat… | ||
| RISC-V Virtual Platforms for Early RISC-V Embedded Software Development | Kevin McDermott, Lee Moore, Hugh O’Keeffe | 10m |
Imperas and Ashling show virtual platforms that let embedded teams start software months before silicon, using a library of over 200 processor models and… | ||
| RISC-V Workshop Barcelona Conclusion | Rick O'Conner | 03m |
Conference closes with thanks to UPC and Barcelona Supercomputing Center for the venue and to organizers Eduardo and Lourdes plus informant team members… | ||
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