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Martin Fink

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titleconferencedate
Unshackling Memory!RISC-V Summit 20192019-12-09
Claimed goal is to unshackle DRAM from the CPU: an open, Ethernet-based coherent memory fabric called Omni Extend that lets accelerators and disparate…
Talk on
Unleashing Innovation from Core to the EdgeOpen Source Leadership Summit 20192019-03-12
Western Digital open-sources a RISC‑V core called swerve core (32‑bit RTL in SystemVerilog) plus an instruction‑set simulator (32/64‑bit) on GitHub, and…
Talk on
Keynote: Unleashing the Power of Data with RISC-V8th RISC-V Workshop Barcelona 20182018-05-07
Western Digital prototypes two in-house RISC‑V cores (a tiny and a small) targeted at SSD controllers, each implemented as a 2-way superscalar in‑order core…
Talk on
Keynote: RISC V – Enabling A New Era Of Open Data-Centric Computing Architectures7th RISC-V Workshop 20172017-11-28
Western Digital commits to transition one billion cores to RISC‑V across its product portfolio, targets first RISC‑V devices around late 2019–2020, and invests…
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