Gajinder Panesar
where else to find them
no profile links on file
what they talk about
where they keep going back
no series more than once — all 3 in the filters
on a stage with
- Anand Joshionce
- Andrea Boccoonce
- Arjun Menononce
all 13 in the filters
who talks about the same things
nobody close enough yet
| title | conference | date |
|---|---|---|
| Every CPU Cycle Counts | RISC-V Summit 2019 | 2019-12-09 |
A compact on‑chip trace encodes cycle‑accurate retirements as run‑length pairs and triplets using Elias gamma encoding and five count tokens called tokens A–E… | ||
| Processor IP Showcase | RISC-V Summit 2019 | 2019-12-09 |
Session collates multiple RISC-V IP offers and concrete claims: market research projects RISC‑V ecosystem hitting about $1B with ~50% CAGR; Andes reports >180… | ||
| It’s Not About the Core, It’s About the System | RISC-V Workshop Chennai 2018 | 2018-07-18 |
Provides a silicon IP suite that adds an orthogonal, non‑intrusive monitoring plane: runtime‑configurable bus monitors, status monitors, trace receivers and a… | ||
| Poster/Demo Previews | RISC-V Workshop Chennai 2018 | 2018-07-18 |
A verification package called Sting test generator produces many randomized configurations per test, runs on simulation, emulation, FPGA and silicon, and finds… | ||
| Debug Specification | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
A RISC‑V debug specification defines a debug module with mandatory abstract commands to read/write GPRs, optional FPR/CSR access, an optional program buffer… | ||
| A Common Software Development Environment for Many-core RISC-V based Hardware and Virtual Platforms | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
Imperas provides an instruction‑accurate simulator that boots Linux in under 10 seconds on a modeled SiFive U54 class core, models peripherals with real‑time… | ||
| nothing matches | ||