Krste Asanovic
where else to find them
what they talk about
all 12 in the filters
where they keep going back
- RISC-V Summit2 editions2019–2022
- RISC-V Summit North America2 editions2024–2025
all 7 in the filters
on a stage with
- Tianrui Wei2×
- Brandon Lewisonce
- Jerry Zhaoonce
all 8 in the filters
who talks about the same things
nobody close enough yet
| title | conference | date |
|---|---|---|
| State of the Union | RISC-V Summit Europe 2026 | 2026-06-08 |
State of RISC‑V is strong: RVA23 ratified Oct 2024 and vendor silicon appears in 2026, under a ratified server platform spec, but parity with incumbents needs… | ||
| Keynote: RISC-V State of the Union | RISC-V Summit North America 2025 | 2025-10-22 |
RISC‑V claims clear momentum: entrenched in embedded, adopted as the default for new AI accelerators, and gaining traction in automotive and server spaces with… | ||
| Keynote: RISC-V State of the Union | RISC-V Summit North America 2024 | 2024-10-22 |
RISC‑V announces RV23 ratified and mandates vectors and hypervisor for application processors, formalizing the jump from RVA20/RV64GC-era binaries to… | ||
| Nerv: Probabilistic Dynamic Partial Order Reduction for Hardware | PLARCH 2023 | 2023-06-17 |
Proposes probabilistic dynamic partial order reduction that records state transitions from warm-up runs, builds a probability table over transaction pairs, and… | ||
| NFC:Next-generation Formal verification for high performance Caches | PLARCH 2023 | 2023-06-17 |
Presents NFC, a formal framework that verifies a multi-banked non-blocking out-of-order data cache and finds 8 bugs in one hour. Uses BMC/abstraction/induction… | ||
| Keynote: State of the Union | RISC-V Summit 2022 | 2022-12-13 |
RISC‑V already ships in billions of cores and vendors are delivering out‑of‑order, superscalar, vector designs that are silicon proven, mapped to newest nodes… | ||
| RISC-V Profiles and Profile Roadmap | RISC-V Summit 2022 | 2022-12-13 |
RISC-V defines concrete ISA bundles so binaries run everywhere: the initial set encodes the de facto distro target (RVA20), a frozen 2022 profile (RVA22) that… | ||
| SiFive Intelligence & VCIX | RISC-V Summit 2022 | 2022-12-13 |
SiFive ships the Intelligence X280 as a full 64-bit applications core with RVV 1.0 vector support and 32 512-bit vector registers, delivering up to 512 bits of… | ||
| Keynote: State of the Union | RISC-V Global Forum 2020 | 2020-09-03 |
RISC‑V claims rapid industry adoption in five years and now manages the ISA spec, golden model and compliance tests while supporting both open and commercial… | ||
| State of the Union | RISC-V Summit 2019 | 2019-12-09 |
Project begins in 2010; a 64‑bit core tapes out in 28nm FD‑SOI 2011 tape-out and Rocket Chip ships by 2012, the Foundation forms in 2015, NVIDIA picks RISC‑V… | ||
| Keynote Panel Opportunity and Risks in Open Source Hardware | RISC-V Summit 2019 | 2019-12-09 |
Panel argues RISC‑V’s value is the open standard vs open-source hardware distinction and shows concrete effects: full SoC projects can hit $100M+ high-end SoC… | ||
| State of the Union: RISC-V | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
Project starts in 2010 and establishes a frozen base ISA with modular extensions, first tape out in 2011 and a Linux port shortly after; foundation forms in… | ||
| Fast Interrupts for RISC-V | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
New task group defines concrete fast-interrupt changes: add configurable per-interrupt privilege/mode, preemption level (3–7 suggested) and priority, provide… | ||
| RISC V State Of The Union | 7th RISC-V Workshop 2017 | 2017-11-28 |
Overview of current RISC-V status and near-term roadmap: the base ISA is base frozen since 2014 and privileged ABI stabilized at 1.10; Linux upstream lands in… | ||
| nothing matches | ||