Chuan Hua Chang
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| title | conference | date |
|---|---|---|
| RISC-V DSP (P) Extension Proposal | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
Proposal defines a RISC-V GPR-based SIMD DSP extension (packed 8/16/32-bit lanes plus non-SIMD 16/32/64 ops) with saturation, rounding and fixed-point support… | ||
| Andes Extended RISC V Features | 7th RISC-V Workshop 2017 | 2017-11-28 |
Andes extends RISC-V with a priority-based preemption CLINT and vectored CLINT that pass interrupt IDs to targets and store 32-bit vector addresses to reach a… | ||
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