Yunsup Lee
where else to find them
what they talk about
all 5 in the filters
where they keep going back
no series more than once — all 5 in the filters
on a stage with
never shared a talk
who talks about the same things
nobody close enough yet
| title | conference | date |
|---|---|---|
| Taking RISC V into New Markets | RISC-V Summit 2019 | 2019-12-09 |
SiFive announces concrete products and numbers: a u8 series 3‑wide 12‑stage out‑of‑order core that claims 1.5x performance per watt vs ARM Cortex‑A72 and 2x… | ||
| Enabling an Open-Source SoC Design Methodology with Federation Tools | Week of Open Source Hardware 2019 | 2019-06-13 |
Ten years of open‑source SoC work motivates a concrete stack: a git‑based package system, a strongly typed build language, and an IP description format that… | ||
| Leveraging Scala to Build Hardware at Scale | Scale By The Bay 2018 | 2018-11-15 |
SiFive describes a full chip stack written in Scala: Chisel as the hardware construction DSL, the Diplomacy parameter framework and FIRRTL as the compiler that… | ||
| Interview | Scale By The Bay 2018 | 2018-11-15 |
Builds RISC-V processors and RISC-V-based SoCs while using Scala as the hardware construction language, claiming it makes hardware design far more productive… | ||
| HiFive Unleashed: World's First Multi-Core RISC-V Linux Dev Board | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
A 64-bit RISC‑V Linux dev board ships a FU540 SoC with four U54 application cores plus one E51 core running at 1.5 GHz, a 2 MB banked L2, and 8 GB DDR4 on the… | ||
| Keynote: Designing the Next Billion Chips: How RISC-V is Revolutionizing Hardware | Embedded Linux Conference + OpenIoT Summit North America 2018 | 2018-03-12 |
Claims that RISC-V is a free and open RISC‑V ISA and that cloud tooling flips chip design into an API-driven workflow with templates and a third‑party IP… | ||
| nothing matches | ||