RISC-V Based Secure Flight Computer System
summary
Project builds a RISC-V flight SoC called Falcon SoC to replace Pixhawk FMUv6x stacks, targeting one order of magnitude better performance and efficiency for drone flight and mission workloads. Prototype work uses PULP cores on FPGA, plans an on-chip secure subsystem and OpenTitan root-of-trust, and adds crypto ISA extensions and IOMMU-like isolation to address missing MMU, insecure flash keys, and lack of process isolation. Three-year program with EU, Canadian and local partners focuses on porting PX4 and proving end-to-end secure key provisioning and authenticated telemetry.
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chapters (8)
- 0:00Introduction to TII
- 1:49Secure Systems Research Center
- 3:33Secure Autonomous Systems
- 8:07Current Drone Security Challenges
- 10:40Motivation for RISC-V
- 12:28Research Program Overview
- 13:33Project Falcon Goals
- 14:36Summary and Future Plans
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