Performance Interfaces for Hardware Accelerators
Talkat 18th USENIX Symposium on Operating Systems Design and Implementation (OSDI '24) · 2024-07-10..07-12·
summary
Proposes a precise accelerator performance IR called LPN and an open toolchain ltc that converts RTL-derived IR into executable performance interfaces and simulators. Reports LPN models match hardware with ~1.7% average error, generated human-readable interfaces average ~20% error, and the auto-generated simulator runs 1–3 orders of magnitude faster than RTL simulators. Evaluations cover DL, RPC serialization, JPEG decoding, genome alignment, and RMT pipelines; using SMT proofs finds a missing buffer fix that yields a 37% speedup.
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chapters (11)
- 0:00Introduction
- 1:48Why accelerators need interfaces
- 2:31What is a performance interface
- 4:20Deriving interfaces from hardware
- 5:26Latency Petri Nets (LPN) as IR
- 6:31How LPN models performance
- 8:17Building LPN for VTA
- 9:25LPN model accuracy
- 10:28Transforming LPN to interfaces
- 11:51LPN tools beyond interfaces
- 13:17Conclusion
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