Using Pyrope To Create Transformable RISC V Architectures
summary
Implements a new HDL Pyrope and a compiler that emits synthesizable Verilog plus a C++ fast emulator, models RISC-V cores as fluid pipelines with elastic buffers, and automatically collapses or expands pipelines (2, 3, 4, 5 stage variants) without source changes. Collapsing to a single-stage design yields roughly a 4x runtime speedup vs Verilator baseline, the C++ fluid emulator performs competitively with Spike, and Yosys/SAT equivalence checks verify collapsed designs in under two minutes each.
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chapters (9)
- 0:00Introduction to Pyrope
- 1:04Fluid pipelines concept
- 2:30Elastic buffer behavior
- 4:23Pipeline stage collapsing
- 5:52Simulation performance results
- 6:35Spike emulator comparison
- 7:22Synthesis results overview
- 8:49Verification process
- 9:33Pyrope project conclusion
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