Loop Rerolling for Hardware Decompilation
summary
Defines hardware loop rerolling to recover syntactic loops from netlists by combining clone detection with sketch-based program synthesis using Rosette, and introduces the Maki IR as the bridge between nets and HDL. Implementation processes 53 PyRTL/SystemVerilog netlists (Yosys used for synthesis), rerolls loops in 52/53 cases, yields mean simulation speedup of 6x (up to 30x), and reduces artifact size by about 39%, with one large benchmark timing out.
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chapters (9)
- 0:00Hardware decompilation
- 1:25Why it matters
- 3:09Hardware loop rerolling
- 5:15Solution approach
- 6:59Loop identification
- 8:03Rolling loops
- 10:30Performance evaluation
- 12:14Conclusion
- 12:56Q&A
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