Dyno-SV: A new IR-driven open-source RTL synthesis tool
summary
Dyno-SV implements a new IR called Dyno-IR rather than reusing Yosys or MLIR, representing designs from behavioral to gate level and delaying control-flow discard until late lowering. A process/control-flow middle end enables reuse of simulation and synthesis passes and an early share pass reuses mutually exclusive adders to reduce gates, beating Yosys on a naïve core in the authors’ tests. The tool already chains Slang frontend + ABC backend for end-to-end synthesis, is actively developed, and plans a first release at month’s end.
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chapters (9)
- 0:00Dyno-SV introduction
- 1:03Hackable hardware compiler vision
- 2:28MLIR vs custom IR
- 3:54Architecture and naming
- 5:16IR structure and hierarchy
- 6:21Control flow and sharing
- 7:45Performance results
- 8:48Project status and plans
- 10:31Q&A
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