Modular Hardware Design with Timeline Types
summary
Filament implements timeline types to encode when signals are produced and consumed, enforcing timing and structural constraints for statically scheduled pipelines and catching pipeline-imbalance errors at compile time. It exposes invocations tied to clock events and checks initiation interval constraints to prevent resource conflicts. The compiler lowers to Verilog; evaluation finds a handwritten Filament con2D uses fewer registers and DSPs and runs at higher frequency than Etherlink outputs, and composing with Reticle cuts logical-resource use; artifacts are available.
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chapters (10)
- 0:00Modular hardware design
- 1:07Hardware accelerators trend
- 2:09Limitations of hardware tools
- 5:22Timeline types for constraints
- 7:30Pipeline imbalances at compile time
- 8:53Pipelining and initiation intervals
- 10:59Evaluating Filament’s efficiency
- 13:32Modularity versus efficiency
- 14:34Fearless hardware design
- 15:18Q&A
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