TileLink: A Free And Open Source, High Performance Scalable Cache Coherent Fabric Designed...
summary
An open, reduced-message cache-coherent fabric with formal composition guarantees and a tested on-chip serialization: the protocol implements deadlock-free cache block motion, five strictly ascending priorities (A–E) for forward progress, and both TL-UL/TL-UH/TL-C variants. Rocket-chip supplies 30+ public modules (crossbars, adapters, coherence manager, VIP, model checker) and bridges to AMBA; silicon shows it works — taped out twice (FE310 and a multicore chip) and supports off-chip serialized links and directory-based L2s.
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chapters (14)
- 0:00Intro
- 1:59Requirements for a RISC-V bus
- 2:52What about AMBA CHIACE?
- 4:34TileLink: Rolling our own has advantages
- 7:22TileLink: Open Source and In Production
- 10:22TileLink Protocol Conformance Levels
- 13:03Operations are composed of Messages (TL-C)
- 15:28Simplifying Requirement: No agent loops!
- 16:58Simplifying Requirement: Strict Priorities!
- 17:36Simplifying Requirement: Ownership tree!
- 17:55On-chip TileLink Wire Protocol
- 18:43Physically Independent Channel Design
- 19:29Read Operation
- 22:10Conclusion
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