QEMU Based Hardware Modeling Of A Multi Hart RISC V Based FPGA With Execution Contexts Free...
summary
Implements QEMU extensions to model a five-core RISC‑V FPGA SoC so one E51 core boots as a privileged manager and enforces isolation while other cores run Linux, using physical memory protection (PMP) to partition RAM and I/O and routing DMA/peripheral requests through the manager. Adds CLINT and PLIC support, heart synchronization and inter‑processor interrupts, L1/L2 cache modes and a driver for peripheral arbitration. It builds Linux across five harts, is functionally working but slow, and is not yet fully upstream.
AI-written summary · about
chapters (9)
- 0:00Intro
- 0:53SOC with Execution Contexts free from Interference
- 2:18SOC Firmware Architecture
- 4:20E51: Superloop Benefits
- 5:15Emulator Required
- 5:41EMDALO TECHNOLOGIES
- 7:30U54-MC QEMU General Points
- 7:55Adding 1.10 Privilege Specification
- 8:06Multi-HART QEMU
related talks
01h 00mHow to run Linux on RISC-V (with open hardware and open source FPGA tools)
11mDemo: Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips
25mRISC-V ecosystem update
41mQEMU: Emulating Your Way to Success
17mHiFive Unleashed: World's First Multi-Core RISC-V Linux Dev Board
32mDeveloping the RISC-V Hypervisor Extensions in QEMU
24mUniversal Tools for Acceleration, Timing, Integration & Machine Enhancement
20mVirtual Prototypes and Open Source Hardware Design in Research and Education