Using Proposed Vector And Crypto Extensions For Fast And Secure Boot
summary
Proposes RISC‑V vector+crypto instructions that implement a AES single‑op block and vectorized GCM and SHA primitives, with assembly that strip‑mines the same code across implementations. Claims: AES-GCM pipeline runs ~100× faster than scalar (example: 2,000 vs 192,000 cycles), SHA‑256 round drops from ~3,600 to ~100 cycles, a Galois matrix multiply goes from ~180,000 to ~12,000 cycles, and a 64 KB secure‑boot payload verifies in under 1 ms versus ~280× slower before.
AI-written summary · about
chapters (7)
- 0:00Intro
- 0:51Summary of Proposed RISC-V Cryptographic Extensions
- 4:46Galois Counter Mode Using the Proposed Crypto Extensions
- 7:13Vectorizing GHASH
- 10:56SHA-256 Algorithm Summary
- 11:40SHA-256 Vector Assembly Code Example
- 12:40Case Study: WalnutDSA Signature Verification
related talks
16mRISC-V Instruction Set Extensions for Cryptography - From Research to Standardization
19mOn the Efficiency of RISC-V Cryptographic Instruction Set Extensions
21mRISC-V International Security Overview
19mAn Open Source Approach to System Security
33mEfficient Modular Arithmetic using Vectorization on CPUs and GPUs
28mModernizing Kernel Cryptography: From Complex APIs To Streamlined Libraries
40mImplementation
58mFast Cryptographic Code via Partial Evaluation