Implementation
summary
Framework reports a modular pipeline that embeds Paar/BP/Tan–Peyrin heuristics, applies local reduction rules and finds what it claims is the current shortest AES mixcolumn xor implementation (about 91 xors). RSA work gives two practical gains: fast CRT without storing Q^{-1} (batched exponent trick) and two prime-generation shortcuts (CRT-based sampling and quadratic-residue sampling), enabling an RSA-3072 private key stored in ~160 bits. SHA-1 study designs ASIC NP/BD cores, lays out chips, and estimates an ASIC cluster ~\$11M to break 160-bit collisions.
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chapters (25)
- 0:00Intro
- 0:23Lightweight Cipher
- 0:53Linear Layer
- 3:14BP Algorithm
- 6:01Rule 9/10/11
- 6:42Framework
- 7:57Example
- 10:29Applications to Cipher Matrices
- 11:29Prime generation problem
- 12:22How to generate random primes: trial division
- 13:24How to choose a random number coprime to M?
- 14:24Improved CRT for random number generation
- 15:20Prime generation using quadratic nonresidues
- 17:13RSA with Chinese Remainder Theorem
- 23:48Hash Functions and Collision Resistance
- 25:15Chosen-Prefix Attack
- 25:37Collision Search in Functional Graphs
- 26:10Differential Cryptanalysis of SHA-1
- 27:15Solution Tree
- 27:54SHA-1 Attack Cores
- 28:56ASIC System Architecture
- 29:23Design and Simulation Flow
- 29:38Simulations and implementation
- 32:00Cost of building the machine
- 32:59Research Questions
