PicoSoC: How We Created A RISC V Based ASIC Processor Using A Full Open Source Foundry Targeted...
summary
Full open-source flow produces a RISC-V ASIC targeted to a 180 nm foundry using PicoRV32 and tools Yosys, Vesta, Greywolf, Qrouter, magic, netgen, Icarus and ngspice. Layout fits ~1 mm² core in a ~2 × 1.5 mm chip with SRAM in a separate macro and pad frame analog cells. Xspice co-simulation runs ~400 µs of CPU time over two days and verifies a 32-instruction boot that zeroes registers and toggles a GPIO. Fabrication via shuttle run is available through the open-source toolchain.
AI-written summary · about
chapters (7)
- 0:00Introduction to eFabless
- 0:36Open-source tool chain
- 2:49Picorv32 SoC design
- 4:28Simulation and verification
- 7:45Layout and chip assembly
- 8:39Efabless platform services
- 10:52Design flow summary
related talks
44mASICone, from Verilog to GDSII with open source tools
11mDriving SoC Innovation with Synopsys RISC-V Solutions
41mRISC-V and Open Source Hardware BoF
41mA Survey of E31 RISC-V Core Floor-Plan and Its Impact on Power, Performance and Area (PPA)
17mRISC-V Meets 22FDX: an Open Source Ultra-low Power Microcontroller Platform
29mOpen Source Processor IP for High Volume SoCs
37mWhy go RISC-V-y?
09mExploring RISC-V architectures with VPSim, a virtual prototyping environment