Tim Edwards
where else to find them
no profile links on file
what they talk about
where they keep going back
- Latch-Up2 editions2024–2026
on a stage with
- Alex Bradburyonce
- Andrew Katzonce
- Anton Klotzonce
all 4 in the filters
who talks about the same things
- Staf Verhaegen9 talks
- Peter Birch3 talks
- Rob Taylor4 talks
- Thomas5 talks
- David Ryan5 talks
- Olof Kindgren14 talks
| title | conference | date |
|---|---|---|
| Post-Efabless Silicon on SkyWater, GlobalFoundries, and IHP | Latch-Up 2026 | 2026-05-01 |
Five chips are submitted to Cadence’s first Sky130 shuttle to recover tapeouts lost after Efabless shuts down, then designs are ported to GF180MCU on… | ||
| CACE Study: Open source analog and mixed-signal design flow | Latch-Up 2024 | 2024-04-19 |
CACE (Circuit Automatic Characterization Engine) is an open source Python flow (available via pip install cace) that verifies analog/mixed‑signal designs using… | ||
| Protecting proprietary data in an open environment | Week of Open Source Hardware 2019 | 2019-06-13 |
efabless runs an open design platform that keeps foundry and third‑party secrets by splitting files into privileged/non‑privileged tech files, exposing only… | ||
| Panel Discussion: Open Source Licensing | Week of Open Source Hardware 2019 | 2019-06-13 |
Panel debates concrete tensions: license text ambiguity forces legal interpretation and risks incompatible OHL variants when projects try to redefine scope… | ||
| Bootstrapping a real working design flow | Week of Open Source Hardware 2019 | 2019-06-13 |
History and current state of a usable open-source verilog-to-GDS flow that stitches together qflow, qrouter and Graywolf with modern tools like Yosys + ABC… | ||
| PicoSoC: How We Created A RISC V Based ASIC Processor Using A Full Open Source Foundry Targeted... | 7th RISC-V Workshop 2017 | 2017-11-28 |
Full open-source flow produces a RISC-V ASIC targeted to a 180 nm foundry using PicoRV32 and tools Yosys, Vesta, Greywolf, Qrouter, magic, netgen, Icarus and… | ||
| nothing matches | ||