Bootstrapping a real working design flow
summary
History and current state of a usable open-source verilog-to-GDS flow that stitches together qflow, qrouter and Graywolf with modern tools like Yosys + ABC, OpenROAD placer and OpenSTA; it handles synthesis, placement, routing, parasitic extraction and STA, reaches tens of thousands of gates today, produced a working Raven SoC taped out in 180 nm running ~100 MHz, but DRC/LVS fixes and manual MAGIC cleanup remain necessary.
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chapters (7)
- 0:00Start
- 7:45Gui Interface
- 9:47Gui
- 12:09Clock Tree Synthesis
- 13:45Static Timing Analysis
- 16:34Summary
- 18:13Floor Planner
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