Developing a Secure Core
summary
Developing a Secure Core examines building processor cores with security as a primary goal, focusing on hardware features and design practices that prevent common vulnerabilities. It covers techniques such as security-oriented ISA extensions, hardware-enforced isolation, and secure boot mechanisms, and discusses applying these approaches in open-source CPU projects like RISC-V.
AI-written summary · about
chapters (4)
related talks
09mThe Future of Embedded Security with RISC-V
45mThe Future of Security is in Open Silicon
19mAn Open Source Approach to System Security
18mCPU Security in the Context of RISC-V
13mRISC-V: Securing the Future of Open Source Computing
15mCore slicing: closing the gap between leaky confidential VMs and bare-metal cloud
16mKeynote: RISC-V Security - Current Initiatives and Future Trends
46mRethinking Architectures and Abstraction for a World Where Security Improvements Matter More than Performance Gains