Week of Open Source Hardware 2019
2019-06-13..2019-06-14
Zurich, Switzerland
| title | author | length |
|---|---|---|
| CERN Open Hardware Licence 2.0 | Andrew Katz | 24m |
CERN OHL v2 is a beta three variants license suite (strong reciprocal, weak reciprocal, permissive) that targets ASICs and FPGAs by defining an available… | ||
| How to create a culture of hardware sharing in academia | Luis Felipe R. Murillo | 21m |
An academic journal called Journal of Open Hardware creates a publication format, the HW metapaper, that requires full build files (Gerbers, mechanical CAD… | ||
| Protecting proprietary data in an open environment | Tim Edwards | 27m |
efabless runs an open design platform that keeps foundry and third‑party secrets by splitting files into privileged/non‑privileged tech files, exposing only… | ||
| Open source hardware licensing: a lowRISC experience report | Alex Bradbury | 18m |
lowRISC reports sticking to upstream licenses (original Rocket was BSD then Apache) and now releases new IP under Apache 2.0, uses CC‑BY for documentation, and… | ||
| Panel Discussion: Open Source Licensing | Alex Bradbury, Tim Edwards, Luis Felipe R. Murillo, Andrew Katz, Anton Klotz | 26m |
Panel debates concrete tensions: license text ambiguity forces legal interpretation and risks incompatible OHL variants when projects try to redefine scope… | ||
| Challenges and opportunities for Open Source Hardware in academia and industry: Opening remarks | Avi Mendelson | 05m |
Presented by Prof. Avi Mendelson at WOSH - Week of Open Source Hardware
Week of Open Source Hardware - a FOSSi Foundation Event… | ||
| RISC-V Adoption in open source implementations, a personal perspective | Rick O'Connor | 23m |
An initiative forms to take ETH Zurich cores (the Ariane and Rocket cores) out of university repos and into industry by providing commercial-grade… | ||
| European Processor Initiative | Mario Kovač | 24m |
A Europe-wide program launches a family of HPC-grade chips aimed at both supercomputers and automotive class‑4/5 workloads, coordinating 26 partners and… | ||
| EPI and beyond: perspectives of a European supercomputing center on opensource hardware and software | Mauro Olivieri | 32m |
Barcelona Supercomputing Center leads RISC‑V RTL and circuit work for EPI, targeting a RISC‑V vector accelerator test chip and a compiler based on the LDM… | ||
| From Research Idea to Business: The ZeroPoint Story | Per Stenström | 19m |
Presented by Per Stenstrom at WOSH - Week of Open Source Hardware
Week of Open Source Hardware - a FOSSi Foundation Event: https://fossi-foundation.org/wosh | ||
| Developing a Secure Core | Anupam Chattopadhyay | 20m |
Presented by Anupam Chattopadhyay at WOSH - Week of Open Source Hardware
Week of Open Source Hardware - a FOSSi Foundation Event… | ||
| Control Flow Integrity on RISC-V | Sylvain Guilley | 27m |
Hardware implementation of control‑flow integrity on RISC‑V enforces Call/Return checks and a shadow stack in silicon, using a parallel metadata cache that… | ||
| Challenges in Open-source RISC-V Implementations: Differentiation & Customization | Zdenek Prikryl | 19m |
A RISC-V IP family called BK3 BK5 BK7 is fully configurable and claimed verified (VM-based coverage and verification plans) and the mandatory RISC-V subset is… | ||
| Challenges and opportunities for Open Source Hardware in academia and industry: Roundtable | 01h 05m | |
Claims a decade of open‑source silicon use in commercial FPGA projects but names infrastructure as the bottleneck: missing IP cores, front‑end parsers, and… | ||
| Bender: A dependency maganement tool for hardware design projects | Fabian Schuiki | 32m |
Bender is a Rust-based package manager that resolves transitive dependency resolution across many git repos, uses semantic versioning and lock files to enforce… | ||
| Ibex and The Mountain of Open Participation: How lowRISC lets everyone participate | Philipp Wagner | 23m |
Ibex is an RV32 two-stage core targeting ARM M0 class area and IPC, with optional I/E/M and compressed ISA and a history from Zero-Riscy. LowRISC updates… | ||
| Complex system simulation and HW/SW co-design with Renode open source simulation framework | Michael Gielda | 24m |
Renode is an open-source, ISS-based simulator and modular framework that runs unmodified OS and embedded images, adds Python scripting and co-simulation with… | ||
| FuseSoC | Olof Kindgren | 18m |
FuseSoC is a package manager and build system for HDL that flattens dependency trees, generates tool-specific setup scripts (Tcl, project files), and can run… | ||
| The role of software in validating silicon IP | Jeremy Bennett | 19m |
Claims that software-only validation missed 13 missing instructions in OpenRISC when the compiler never emitted them, prompting a full UVM analysis; hybrid… | ||
| Enabling an Open-Source SoC Design Methodology with Federation Tools | Yunsup Lee | 35m |
Ten years of open‑source SoC work motivates a concrete stack: a git‑based package system, a strongly typed build language, and an IP description format that… | ||
| FOSSi Foundation Update | Stefan Wallentowitz | 09m |
Founded from grassroots open RISC efforts, the foundation organizes community events since 2012 and incorporates as a UK Community Interest Company in 2014… | ||
| SpinalHDL : Paradigm introduction | Charles Papon | 21m |
SpinalHDL is a Scala library embedding HDL that generates Verilog by running Scala code as an elaborator, letting software data structures create repeated… | ||
| Design Automation in Wonderland: EPFL Logic Synthesis Libraries | Heinz Riener | 22m |
EPFL releases eight modular logic-synthesis libraries implemented in header-only C++14/17 that glue together a truth-table engine (Kitty), a generic network… | ||
| Bootstrapping a real working design flow | Tim Edwards | 24m |
History and current state of a usable open-source verilog-to-GDS flow that stitches together qflow, qrouter and Graywolf with modern tools like Yosys + ABC… | ||
| Cocotb: Python-powered hardware verification | Philipp Wagner | 21m |
Cocotb claims that RTL verification is best written as software and provides a simulator plug‑in that links simulators to Python via VPI/FLI/VHPI. It runs on… | ||
| Introduction to Formal Verification with Symbiotic EDA Open Source Tools | Matt Venn, Clifford Wolf | 46m |
Overview of using Symbiotic EDA open source flow with SymbiYosys (sby), PySMT and SMT/SAT solvers (yices default, Z3, Boolector) to write asserts/assumes and… | ||
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