Packet Manipulator Processor A RISC V VLIW Core For Networking Applications

on YouTube ↗11m

" summary

Claims a RISC‑V VLIW RISC-V core built as a packet processor that implements parsing, routing, ACLs and custom tunneling in hardware‑accelerated pipelines. Uses a protocol‑independent data plane model with per‑packet stages, small on‑core state stores and explicit memory for connection state. Describes an actual silicon/software prototype running on a switch, exposes small on‑core state memory limits and a multicore processing with reordering problem when packets are split across cores, and reports prototype validation and performance tradeoffs.

AI-written summary · about

" chapters (6)

1. 0:00Introduction to PMP
2. 2:02Pipeline stages and packet processing
3. 5:01Switch and router applications
4. 8:01Multi-core processing challenges
5. 10:15High-speed packet handling
6. 11:19Conclusion and Q&A

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