A Tightly Coupled Light Weight Neural Network Processing Units With RISC V Core
summary
A tightly coupled neural accelerator integrates with a Rocket RISC‑V core via custom RISC‑V coprocessor instructions and a shared L1/cache interface and exposes MP, DMA and stream instructions for command, parameter load and data movement. Microarchitecture is an 8‑unit 1D systolic array with local storage and a reconfigurable LUT for activations, implemented in 55nm. On an SoC running ApproximateBench/GAP workloads it reports about 2× throughput and >80% energy reduction versus CPU-only.
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